This definitely has to be one of the most interesting projects I’ve been required to undertake as part of my undergraduate degree!
In a nutshell, the project is a “$100 supercomputer challenge”. We are provided a $100 budget, with which we are required to purchase an Altera FPGA (field programmable gate array) chip and related components (SRAM, JTAG interface, DC power supply, etc.) This FPGA is then used to implement a multi-core processor in VHDL, with the aim of outperforming a 2007 Intel Core 2 Duo (utilising MATLAB) at the task of multiplying a 64×64 (32-bit unsigned integer) matrix by its transpose, with discarded overflow.
This is my first ever attempt at PCB design, so needless to say, I am quite happy and proud with the outcome!
PCB schematic, showing top (red) and bottom (blue) layers. Cyclone III FPGA in centre.
3D rendering of PCB.
The next step will involved sending the PCB design off for fabrication (thankfully this process is not included in the $100 budget), designing the multi-core processor… and then the overwhelming joy of soldering ~100 surface mount components. Shannon Fenn (my project partner) and I are still tossing up whether to utilise our previous pipelined processor design (see schematic below), or streamline an earlier single-cycle design to maximise the number of cores we can fit on the FPGA, as the number of available logic elements creates a performance bottleneck. The FPGA we chose is an Altera Cyclone III, with 500 MHz switching speed. This is complemented by a 2 Mb Cypress synchronous SRAM chip, and a 5-level DC power supply (12, 5, 3.3, 2.5 and 1.2 V), which we also designed ourselves. I won’t reveal the exact component models at this stage; it is a competition, after all!
VHDL pipelined processor schematic (2011 ELEC3720 Programmable Logic Design Project (David Budden and Shannon Fenn)).
Check back for updates regarding this project (completed as a requirement for ELEC4700 Advanced Computer Systems, The University of Newcastle (Australia), under the supervision of Dr Steve Mitchell).
well done.that is great project ,
Anyone interested in the outcome of this project should check out my recent article: https://davidbudden.com/multi-core-processor-project-results/
sanely ambitious idea!! Good luck. I just came here looking for something else, but I just wanted to warn you to do some signal integrity or at least to apply some heuristic rules to high speed lines, like data/ address to the SRAM. Also, FPGAs are a bit of a ‘spoiled children’ with regard to power supply. Aren’t you considering power and ground planes in a standard 4-layer layout? Maybe it works without them, but in case you assemble everything and refuse to work (really don’t wish this to you), think about these point. Very few people succeeded at first try, and if so, they were just lucky guys that learnt nothing!!
Thanks a lot for the advice, Joan! Thankfully the issues we had were all quite small (and yes, we had some considerably sized power and ground planes within the PCB). Check out the project results: https://davidbudden.com/multi-core-processor-project-results/
Aw, this was a really qulitay post. In theory I’d like to write like this too – taking time and real effort to make a good article… but what can I say… I procrastinate alot and never seem to get something done.
Nice to read your blog
Very useful blog. Keep up the good work.
Goodmorning , Mr Budden. I have read your project and although (as you already know), I don’t understand a lot of it, but what I do understand is very impressive and I can easily understand that part. Odviously, I can see that you have worked extremely hard on this project, and i will continue to hope that you get all the marks, you believe you deserve, for this project.I am glad that you have really enjoyed this project, and it is always nice to do something new, and enjoy it with your studies. I am very proud and encourage you to continue as hard as you can, with all your hopes and Dreams.
Cheers and keep on enjoying this and having Fun.
From Me